01. What is the Miller Effect?

The Miller effect, also known as the Miller effect, refers to the distributed capacitance or parasitic capacitance between the input and output in an electronic inverting amplifier circuit. Due to the amplification effect of the amplifier, the capacitance equivalent to the input terminal will increase by 1K times, where K is the voltage amplification factor of the amplifier circuit. Although the Miller effect generally refers to the amplification of capacitors, the impedance between any input and other high amplification nodes can also change the input impedance of the amplifier through the Miller effect. Simply put, it refers to the phenomenon where the input impedance of an amplifying circuit changes due to the influence of parasitic capacitance, ultimately resulting in a change in the frequency response of the circuit.

02. Capacitance parameters of MOS transistor

Input capacitor Ciss

DS short circuit, the capacitance between GS measured by AC signal, Ciss is composed of parallel connection of GS capacitor and GD capacitor, i.e. Ciss=Cgs Cgd. When the input capacitor is charged to the threshold voltage, the MOS transistor will turn on, and when it is discharged to a certain value, the MOS transistor will turn off. Therefore, the switching time of Ciss and MOS transistor is closely related.

Output capacitor Coss

GS short circuit, the capacitance between DS measured by AC signal, Coss is composed of parallel connection of GD capacitor and DS capacitor, i.e. Coss=Cgd Cds.

Reverse transmission capacitor Crss

The capacitance between S grounding and GD is Crss=Cgd.

03. Understanding the Miller Effect from the Switching Process of MOS Transistors

t0-t1：

When the driving turn-on pulse is applied to the G and S poles of the MOSFET, it is equivalent to charging the input capacitor Ciss (mainly for Cgs due to Cgs>>Cgd). Due to the presence of the input capacitor, VGS can only rise at a certain slope, which is also a factor limiting the switching speed of the MOSFET; VGS slowly rises to VGS (th), during which the MOS transistor remains in an off state, and a small current has already flowed; The voltage of VDS remains unchanged at VDD.

t1~t2：

When VGS reaches VGS (th), MOS begins to conduct, and the gate voltage continues to charge the input capacitor Ciss. The drain begins to flow current ID, and as VGS increases, ID gradually increases while VDS remains at VDD; During the switching process of the power MOS transistor, the power consumption is relatively high at this stage, reaching its maximum at the VGP point, but the duration is relatively short.

t2~t3：

When the VGS voltage reaches VGP and ID reaches its maximum value, VDS begins to decrease, and the voltage on CGD also decreases. This is accompanied by the discharge of CGD, and the gate current is basically used for the discharge of CGD, keeping the gate voltage of MOSFET basically unchanged. At this time, we enter the Miller plateau period (Miller plateau is the time period during which the VGS voltage remains unchanged during the charging and discharging process of GS), and the existence of Miller plateau increases the switching time and switching loss.

t3~t4：

CGD discharge is completed, Miller platform ends, VDS continues to decrease, ID remains unchanged, and MOSFET base is fully conductive.

04. Measures to reduce the Miller effect

To reduce the impact of Miller effect on MOS switching speed, the following measures can be taken:

Choose MOS transistors with smaller Cgd;

1. Increase the driving voltage to avoid the phenomenon where the driving voltage is critical to the platform voltage;

2. Enhance the driving capability of control signals;

3. Reduce the VDD voltage.